The present invention relates generally to the field of processors and in particular to predicting an unaligned memory access in a pipelined processor.
Portable electronic devices have become commonplace. Two trends in portable electronic devices are increased functionality and decreased size. Increased functionality is facilitated by increased computing power provided by faster and more powerful processors.
As well as providing advanced features and functionality, portable electronic devices themselves continue to shrink in size and weight. One impact of this shrinking trend is the decreasing size of batteries used to power the processor and other electronics in the device. While increases in battery technology partially offset the problem, the decreasing size of batteries imposes a strict power budget on all portable electronic device electronics. A significant portion of the power budget of portable electronic devices is power consumed by the processor.
Hence, processor improvements that increase performance and decrease power consumption are desirable for many applications such as portable electronic devices. Commonly modern processors employ a pipelined architecture, where sequential instructions, each having multiple execution steps, are overlapped in execution. For maximum performance, the instructions should flow through continuously through the pipeline. Any situation that causes instructions to be flushed from the pipeline, and subsequently restarted, can detrimentally impact both performance and power consumption.
Some pipeline resources, such as queue locations for instruction status and tracking, are allocated as the instruction enters the pipeline. If it is discovered later in the pipeline that a single instruction requires more resources than originally allocated, subsequent instructions may need to be flushed to allow their resources to be reallocated to the instruction that needs them.
A memory access instruction loading or storing misaligned data from or to memory is one example of an instruction that may need more pipeline resources than were originally allocated to it, the discovery of which may not occur until deep in the pipeline. Misaligned data are those that, as they are stored in memory, cross a predetermined memory boundary, such as a word or half-word boundary. Due to the way memory is logically structured and addressed, and physically coupled to a memory bus, data that cross a memory boundary commonly cannot be read or written in a single cycle. Rather, two successive bus cycles may be required—one to read or write the data on one side of the boundary, and another to read or write the remaining data.
A memory access instruction—that is, a load or store instruction—to unaligned data must generate an additional instruction step, or micro-operation, in the pipeline to perform the additional memory access required by the unaligned data. However, the alignment of the data cannot be determined until the effective address of the memory access and the data size are known, which may occur only deep in the pipeline, in an execute stage. By the time the effective address is generated and the misalignment of the data is discovered, there may be insufficient pipeline control resources available to generate a micro-operation to perform the second memory access. In the case of such misalignment, the pipeline must be flushed of at least all following instructions, to free up such resources. The flushed instructions must then be re-fetched and re-executed in the pipeline, degrading processor performance and wasting power.